Let’s Build a Chip – With Math

We have been writing a lot lately about Internet companies building their own home-grown semiconductors (more here and here and here). And we have been getting a lot of questions about how much it costs to do this. So in this post – math!

Semiconductor costs are an exercise in applied geometry. The foundries which manufacture the chips charge by the wafer. These are large (300mm diameter) discs of the purest silicon. Companies design chips to have certain functions, then lay those out in the form of circuits. The foundry then etches those circuits onto the wafer as many times as they fit. Design a big chip, and you do not get many chips per wafer. Design a small chip… you get the idea. There are a few other factors at play, but they are mostly functions of this basic math. As a side note, this is the source of the economic power of Moore’s Law. Every advance in manufacturing (process node) shrinks the size of those circuits which means you can fit more of them on the wafer and thus get more chips for the same wafer.

Those are the variable costs of a chip, but there are some big upfront, fixed costs. These are dominated by two expense buckets – people and intellectual property (IP).

The IP really comes in two forms – content libraries and design tools. The libraries cover things like on-chip memory, input and out (I/O) circuits and libraries of common functions (e.g. Arm processors). These are typically priced as an upfront license and then per chip royalties. And they are not cheap, an Arm license costs tens of millions upfront – and they are generally unavoidable. Design tools, commonly referred to as Electronic Design Automation (EDA) tools are software that help designers lay out circuits and then simulate and verify the final performance of those chips. Crucially, these tools are designed to tightly couple with the work flow systems of the Foundries, where the chips are physically manufactured. As a result, the EDA market is highly concentrated, with three firms effectively cornering the market through which all chips must pass.

And while all that IP is expensive, the bill for engineers is much higher. If you started a company to design a chip, and ran it lean, you could theoretically get a chip ready for production for under $20 million, we have seen it done for less than $10 million. But if you are a big company, with a complex roadmap, you will likely need many more people. Other than general corporate bloat, the big difference between those two extremes is the need for software engineers to make sure the chip works well with the software that will run on it and cover all the corner cases. For a company like Apple, the chip team needs to make sure the chip is tightly coupled with iOS and MacOS, and all the other OS’s – this is complex, often labor-intensive work.

To greatly oversimplify, a chip team will need some core engineers, working on the heart of the product – for a CPU this will be the architects and engineer laying out the basic functions. Then factor in other teams for handling I/O, memory, on-chip communications, etc. This team could easily be 100-200 people, but it varies tremendously based on what the chip is supposed to achieve. Google’s YouTube built their VCU with a design team of 50 people, many of whom seem to have had full-time software roles supporting YouTube itself. By contrast, Apple is building their own 5G modem. As part of this they acquired 1,000 modem engineers from Intel and opened up a campus in San Diego to poach 2,000 people from Qualcomm. So that’s at least 3,000 people just to build a modem. In fact, one of our favorite mysteries in semis today is calculating just how big the Apple Silicon team is. Many people attribute Apple’s rise in silicon to its acquisition of PA Semi in 2008, but our sense is that PA Semi was just a small part of the process. Apple’s second largest R&D center is in Israel. We believe that is where the heart of the Silicon work is done. In 2015 that site had 700 employees, and has to be much larger now. Currently Apple has 147 job openings in Israel alone, a quick scan looks like most of those are silicon-related jobs. We digress. Our point is that while these design teams can vary in size, a rough rule of thumb is that these teams can easily number 300-400 for a relatively simple product, and can quickly become much larger.

Beyond that core team, we also need software engineers and these teams are usually far larger than the core team, as we noted this is labor intensive work with lots of back and forth with our teams. Then there are teams of people to wrangle from design to production. The big chip companies have hundreds of people handling operations. The non-chip companies often work with third parties, often called “ASIC vendors”, which are other chip companies who already have big operations teams doing this work.

There is also a considerable time lag between the time the designers release the design to the foundry, aka the Tape Out, and that chip going into production. Some of that time is spent by the foundry getting their process and tooling in place. But an even larger amount of time is spent going back and forth between the designers and the foundry fixing bugs. There are always defects. Best case, these are introduced in the manufacturing process, the big foundries are really good at analyzing those defects and ironing them out. (This phase is a big part of the reason that TSMC is so far ahead of everyone else.) The worst case is the team discovers some type of bug that forces some amount of rework. Most of the time these occur there is a fairly simple fix, but sometimes they can force a redesign of the entire product. The latter situations are fairly uncommon at well-run chips companies, but frequent enough to keep people awake at night until the chip comes back and is spun up in the home lab.

Finally, the chip is ready to go into production. The chip designer then have to deliver their production forecast and commit to orders. This is high risk, and is sometimes called “Risk Starts” for a good reason. In the case of Apple, ordering the A Series applications processor, they have to forecast months into the future, with staggeringly large orders. For the iPhone, Apple is likely committing to orders of 50 million to 100 million chips, just to get started. That is easily several billion dollars.

Here are the numbers:

First, some fixed costs. A team of 460 costs around $170 million a year, fully loaded. As we noted above, this amount can vary widely from 20 to 5,000. Our guess is that Apple’s team is now massive, thousands of people, while Google’s is fairly modest, but a start-up could do this with 20 people. The other thing to note is that “Tape Out costs” this is grab-bag of various elements including upfront fees to the foundries and partners, consultants, testing, expediting shipments, moderate re-work and debugging, etc. This amount can also vary considerably, but we usually see it measured in tens of millions of dollars.

The cost per chip (known good die aka KGD) is the key variable component of this exercise. We added several types of chips to give a sense of how these can range. The sizes for the A14, M1 and TPU are all based on the latest data we could find publicly available. The GPU and CPU sizes are rough averages based on some of the most recent chips. These chips can be much larger, especially in the data center. For die per wafer, we used an online calculator, thank you Caly Technologies. And then we made some guesses for the range of leading edge wafer costs.

Finally, we looked at minimum order quantities. In our experience, people always forget about this cost, it seems to have some sort of SEP Field clouding it. Employees at big corporates do not like to discuss these because they are such large numbers that everyone knows there is an endless slog of meetings and approvals to wade through before getting spent. And this is where a lot of start-up chip companies founder. They have a great product, but now they need to go raise a whole new funding round to actually produce it – literally betting the company.

Add it all up and it should be clear that designing a chip is something very few non-chip companies can really do. Apple Silicon has to cost Apple billions every year, before we even get to working capital for the chips. Even Google has to be carefully weighing which chips it is going to produce. There are also several important risks that come with this. We are working on a follow-up post to look at those, but one thing really jumps out at us from these numbers. Once companies start spending these amounts there is a strong tendency to stick with the internal solution. Internal chip capabilities come with big sunk cost issues. The industry is littered with the remains of companies that held themselves hostage to their internal fixed costs – Nokia and its manufacturing plant is just the first to come to mind. Building internal silicon obviously comes with significant financial costs, but companies need to also weigh the cultural and strategic gravity they create.

Photo by Annie Spratt on Unsplash

4 responses to “Let’s Build a Chip – With Math

  1. Good to see this analysis attempted. You cover things that people often forget. However, there’s are a couple of problems with your “defect rate”. First, the name is a little misleading, it should be something like (1 minus) “(die) yield”, as “defect rate” is used for a property of the manufacturing process (at a particular point in time). Second, the yield depends critically on die size. The larger the die, the lower the yield. Large dies get hit three times – more area so less die per wafer, more die wasted around the edge of the wafer, and worse yield per die. This Quora answer (https://www.quora.com/What-is-a-typical-value-for-good-yields-in-a-semiconductor-fabrication-process/answer/John-Kim-6) gives a pretty good rationale for yield behaviour.

    • You’re right. I really oversimplified that part. In my defense, a big part of the motivation for that was I find this topic so interesting that I risked swamping the whole piece with that discussion. I could have doubled the post’s length with just that discussion. And thanks for reading

  2. The Apple silicon division is indeed massive, but an order of magnitude smaller than say Intel or Qcom. There are tens of different R&D groups, but only handful of teams for foundry relations/ATE ,verification (the real heroes in any silicon project), validation, etc.

    Amazing they do so much with so little really

    • That’s a really good point. I always say that Apple is the best run semiconductor company in the business, and they’re not really a semiconductor company.
      “Amazing they do so much with so little”

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