Ten or so years ago, when Amazon stock was still in double digits and no one really knew what The Cloud was, the software world saw the phenomenon known as “Stealth IT”. The idea was the software programmers, especially inside large corporations, wanted to experiment with code, but their codebase was complex and tightly guarded. So these rogue programmers would use their corporate credit cards to buy a few hours of AWS time. Here they would test out their ideas, and once working, bring the completed code to their bosses and argue for its implementation. This whole process has become a software segment in its own right, with multi-billion companies providing tools for managing this. And of course, all those corporate code bases ended up in the public cloud anyway.
What if we could do something similar with semis?
Producing a chip today is cumbersome. The actual design process is fairly straightforward. There are a number of free and/or open source design tools available. But the process basically stops there. Having an actual physical chip is important to verify that the design actually performs as expected. There are software tools that get most of the way there, but ultimately there is no substitute for having the actual, physical chip. There are foundries who would happily produce a chip for you, but even the smallest and hungriest will ask for upfront payments measured in the thousands or tens of thousands of dollars. And they are not being stingy. Every wafer that passes through their system are a real expense.
Generally speaking foundries do not like to produce test chips. Maybe you want a dozen chips to play around with, but the wafer required for that can fit hundreds, maybe thousands of chips. It makes no sense to produce a wafer for just a handful of chips. Some foundries will make a “pizza”, which combines chips from several customers on one wafer. This solves the wasted wafer problem, but is still a hassle for everyone. And by hassle we mean someone has to pay for something.
A while back we linked to this video from a Google engineer working on open source chip design. Read what you want into his and Google’s ultimate ambition here, but a few things stand out. First, he provides a good list of all the open source design tools available for designing a chip. Second, it looks a lot like Google is promoting experimentation here. Further evidence can be found in Google’s work with US foundry Skywater and Google’s more recent announcement of Global Foundries’ participation in this program.
Put simply, this looks like a path to Stealth Semis. There are still some costs involved (although there is that “Free Tape Out” offer floating out there on the Internet that no one quite understands). Regardless, it is getting easier (and cheaper) to design a chip just for ‘fun’.
Now a few caveats. First, this is not a leading edge process. Skywater is offering their 130nm and Global Foundries their 180nm process, so pretty far from leading edge. And from what we can tell, the open source tools behind this are still fairly rough around the edges.
Nonetheless, there is plenty of utility in what they are offering. There are still many chips being built on trailing edge processes like this. In the Google/GF announcement they have this to say about global demand for 180nm:
Specifically, applications using 180nm are at a global capacity of 16+ million wafers a year and bound to grow to 22+ million wafers in 2026, according to GlobalFoundries.
Source: Google
And we can assume that 130nm is in the same ball park. It is unclear how much of that is for new designs. It may just be legacy applications with a very long shelf life (looking at you automotive).
That being said, there is still immense utility in this. Prototyping chips is a painful process requiring considerable effort from everyone involved. Having physical samples to play with can be incredibly useful. This is especially true for analog parts where precise calibration of power levels is crucial. And what process sees a lot of analog parts – trailing edge like 130nm and 180nm. Analog parts do not scale with Moore’s Law the same way digital chips like CPUs and GPUs do, and thus often work perfectly well with older processes.
Now admittedly we are still stuck with the pizza wafer problem, but we hearing rumors about interesting alternatives here, and even without that it is clear that some of the trailing edge fabs are becoming more accommodating to very small volume customers. Their costs for running each wafer are much lower, and they rightly recognize that once someone prototypes a chip on one process they are very likely to stick with that process when it comes time for production volume.
Semis are changing, so it makes sense that new customer acquisition models are going to emerge as well.